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| author |   Bastien Curutchet <bastien.curutchet@bootlin.com> | 2024-04-02 09:12:12 +0200 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2024-04-09 16:58:42 +0100 |
| commit | 609302ca04a3177463b0fbf4d5fc55a3ab4f900d (patch) | |
| tree | bb36d722e2b706b26a30b1c1b825e880626cb8d6 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: ti: davinci-i2s: Add S24_LE to supported formats (diff) | |
| download | wireguard-linux-609302ca04a3177463b0fbf4d5fc55a3ab4f900d.tar.xz wireguard-linux-609302ca04a3177463b0fbf4d5fc55a3ab4f900d.zip | |
ASoC: dt-bindings: davinci-mcbsp: Add the 'ti,T1-framing-{rx/tx}' flags
McBSP's data delay can be configured from 0 to 2 bit clock periods. 0 is
used for DSP_B format, 1 for DSP_A format. A data delay of 2 bit clock
periods can be used to interface to 'T1 framing' devices where data
stream is preceded by a 'framing bit'. This 2 bit clock data delay is
not described in the bindings.
Add two flags 'ti,T1-framing-[rx/tx]' to enable a data delay of 2
bit clock periods in reception or transmission.
Signed-off-by: Bastien Curutchet <bastien.curutchet@bootlin.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Link: https://msgid.link/r/20240402071213.11671-13-bastien.curutchet@bootlin.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions