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| author |   Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-10-06 13:39:58 +0300 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-10 09:27:08 +0200 |
| commit | 62b1feac485866494f111e3a6aa4a9ae03a7a2b9 (patch) | |
| tree | 6de93893edf441bc786fd46e005873aafa7dcf83 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: rzg2l: Refactor SD mux driver (diff) | |
| download | wireguard-linux-62b1feac485866494f111e3a6aa4a9ae03a7a2b9.tar.xz wireguard-linux-62b1feac485866494f111e3a6aa4a9ae03a7a2b9.zip | |
clk: renesas: rzg2l: Add divider clock for RZ/G3S
Add a divider clock driver for RZ/G3S. This will be used on RZ/G3S for
the SDHI, SPI, OCTA, I, I2, I3, P0, P1, P2, and P3 core clocks.
The divider has some limitation for SDHI, OCTA and SPI clocks:
- SDHI div cannot be 1 if parent rate is 800MHz,
- OCTA, SPI div cannot be 1 if parent rate is 400MHz.
To handle these limitations, a notifier is registered from platform
specific clock driver, which makes sure proper actions are taken before
the clock rate is changed, when needed.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231006103959.197485-4-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions