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| author |   Douglas Anderson <dianders@chromium.org> | 2016-06-20 10:56:48 -0700 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2016-06-22 18:24:05 +0200 |
| commit | 64e3481c8ab187a42b68048dbd321e54d182e762 (patch) | |
| tree | e5d6e7c15a3c61eabf003b64cb6805946fb2f4ec /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: rockchip: fixes the gic400 2nd region size for rk3368 (diff) | |
| download | wireguard-linux-64e3481c8ab187a42b68048dbd321e54d182e762.tar.xz wireguard-linux-64e3481c8ab187a42b68048dbd321e54d182e762.zip | |
arm64: dts: rockchip: Add soc-ctl-syscon to sdhci for rk3399
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions