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| author |   Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-10-11 15:26:06 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2016-11-05 23:21:31 +0900 |
| commit | 64f4896592b5ac830bc0c7daf91ea21100eb54be (patch) | |
| tree | 4b354e09ae23e8760ea4070ee34ff3a1b3d000ab /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: uniphier: remove redundant serial fifo-size properties (diff) | |
| download | wireguard-linux-64f4896592b5ac830bc0c7daf91ea21100eb54be.tar.xz wireguard-linux-64f4896592b5ac830bc0c7daf91ea21100eb54be.zip | |
ARM: dts: uniphier: add clocks/resets to EHCI nodes of sLD3 SoC
Now, the clock/reset controller driver is available for this SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions