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author | 2018-12-19 15:55:28 -0800 | |
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committer | 2019-04-25 23:22:26 -0500 | |
commit | 6969d1d9c61524d3ce492cfdca92d5dfa51e2e54 (patch) | |
tree | d7cf95198ddd9849185622ae4c7cc18bdd0bfb2b /tools/perf/scripts/python/export-to-postgresql.py | |
parent | ARM: dts: qcom: ipq4019: enlarge PCIe BAR range (diff) | |
download | wireguard-linux-6969d1d9c61524d3ce492cfdca92d5dfa51e2e54.tar.xz wireguard-linux-6969d1d9c61524d3ce492cfdca92d5dfa51e2e54.zip |
ARM: dts: qcom-apq8064: Set 'cxo_board' as ref clock of the DSI PHY
Add 'xo_board' as ref clock for the DSI PHY, it was previously
hardcoded in the PLL 'driver' for the 28nm 8960 PHY.
Signed-off-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Andy Gross <agross@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions