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| author |   Dmitry Osipenko <digetx@gmail.com> | 2019-06-03 21:59:42 +0300 |
|---|---|---|
| committer |   Daniel Lezcano <daniel.lezcano@linaro.org> | 2019-06-25 19:49:18 +0200 |
| commit | 6b349c3624d230f4bd692d57d8203a407f52b646 (patch) | |
| tree | de6730ff106e00742ab025e5f3ab233db7c1d6ca /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clocksource/drivers/tegra: Reset hardware state on init (diff) | |
| download | wireguard-linux-6b349c3624d230f4bd692d57d8203a407f52b646.tar.xz wireguard-linux-6b349c3624d230f4bd692d57d8203a407f52b646.zip | |
clocksource/drivers/tegra: Replace readl/writel with relaxed versions
The readl/writel functions are inserting memory barrier to ensure that
outstanding memory writes are completed, this results in L2 cache syncing
being done on Tegra20 and Tegra30 which isn't a very cheap operation.
Replace all readl/writel occurrences in the code with the relaxed versions
since there is no need for the memory-access syncing.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions