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| author |   Christophe Leroy <christophe.leroy@c-s.fr> | 2019-05-10 09:24:48 +0000 |
|---|---|---|
| committer |   Michael Ellerman <mpe@ellerman.id.au> | 2019-07-05 01:35:10 +1000 |
| commit | 6c5875843b87c3adea2beade9d1b8b3d4523900a (patch) | |
| tree | 3654d6521c3ba3692ad8e73abd3b05b519dd1527 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | powerpc/mm/hugetlb: Don't enable HugeTLB if we don't have a page table cache (diff) | |
| download | wireguard-linux-6c5875843b87c3adea2beade9d1b8b3d4523900a.tar.xz wireguard-linux-6c5875843b87c3adea2beade9d1b8b3d4523900a.zip | |
powerpc: slightly improve cache helpers
Cache instructions (dcbz, dcbi, dcbf and dcbst) take two registers
that are summed to obtain the target address. Using 'Z' constraint
and '%y0' argument gives GCC the opportunity to use both registers
instead of only one with the second being forced to 0.
Suggested-by: Segher Boessenkool <segher@kernel.crashing.org>
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions