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| author |   Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-02-17 16:06:27 +0100 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-03-06 10:31:15 +0100 |
| commit | 6c950c20da38debf1ed531e0b972bd8b53d1c11f (patch) | |
| tree | 270dbb882afef90edd62380add248fbfdf4741bf /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: exynos: add ports to TC358764 bridge on Arndale (diff) | |
| download | wireguard-linux-6c950c20da38debf1ed531e0b972bd8b53d1c11f.tar.xz wireguard-linux-6c950c20da38debf1ed531e0b972bd8b53d1c11f.zip | |
ARM: dts: exynos: fix WM8960 clock name in Itop Elite
The WM8960 Linux driver expects the clock to be named "mclk". Otherwise
the clock will be ignored and not prepared/enabled by the driver.
Cc: <stable@vger.kernel.org>
Fixes: 339b2fb36a67 ("ARM: dts: exynos: Add TOPEET itop elite based board")
Link: https://lore.kernel.org/r/20230217150627.779764-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions