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| author |   Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> | 2017-10-13 06:03:06 +0000 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2017-10-13 11:19:01 +0100 |
| commit | 6cba3fa98cdd045e020f096bb8888225d3906895 (patch) | |
| tree | 348b9a019fa1be57af73674c7b057aedab730015 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: rsnd: add rsnd_kctrl_xxx() macro (diff) | |
| download | wireguard-linux-6cba3fa98cdd045e020f096bb8888225d3906895.tar.xz wireguard-linux-6cba3fa98cdd045e020f096bb8888225d3906895.zip | |
ASoC: rsnd: more clear ADG clock debug info
ADG inputs clock from CLK{A,B,C,I} and outputs clock from
CLKOUT{0,1,2,3} which is selected by BRG{A,B}.
Now, ADG is assuming BRGA is for 44100Hz related clocks,
BRGB is for 48000Hz related clocks.
Clock related debug is very difficult/confusable.
This patch cleanups clock related debug info.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions