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| author |   Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> | 2019-10-22 22:30:22 +0530 |
|---|---|---|
| committer |   Vinod Koul <vkoul@kernel.org> | 2019-11-06 22:38:02 +0530 |
| commit | 6ccd692bfb7fc44a6b4acd97874d8be78ecb5c91 (patch) | |
| tree | 58a37ed16bd73b3d0ccd1bb7b7500cc937720691 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dmaengine: xilinx_dma: Extend dma_config struct to store irq routine handle (diff) | |
| download | wireguard-linux-6ccd692bfb7fc44a6b4acd97874d8be78ecb5c91.tar.xz wireguard-linux-6ccd692bfb7fc44a6b4acd97874d8be78ecb5c91.zip | |
dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support
Add support for AXI Multichannel Direct Memory Access (AXI MCDMA)
core, which is a soft Xilinx IP core that provides high-bandwidth
direct memory access between memory and AXI4-Stream target peripherals.
The AXI MCDMA core provides scatter-gather interface with multiple
independent transmit and receive channels. The driver supports
device_prep_slave_sg slave transfer mode.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions