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author | 2019-08-16 17:27:55 -0700 | |
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committer | 2019-08-16 17:27:55 -0700 | |
commit | 6e625a1a3f471d63989d3a66cdf6a0c307654848 (patch) | |
tree | 02f1e71eab7280762248880f0decdd1180a61c83 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux (diff) | |
parent | xtensa: add missing isync to the cpu_reset TLB code (diff) | |
download | wireguard-linux-6e625a1a3f471d63989d3a66cdf6a0c307654848.tar.xz wireguard-linux-6e625a1a3f471d63989d3a66cdf6a0c307654848.zip |
Merge tag 'xtensa-20190816' of git://github.com/jcmvbkbc/linux-xtensa
Pull Xtensa fix from Max Filippov:
"Add missing isync into cpu_reset to make sure ITLB changes are
effective"
* tag 'xtensa-20190816' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: add missing isync to the cpu_reset TLB code
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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