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| author |   Jiancheng Xue <xuejiancheng@hisilicon.com> | 2016-10-29 14:13:37 +0800 |
|---|---|---|
| committer |   Stephen Boyd <sboyd@codeaurora.org> | 2016-11-11 15:43:49 -0800 |
| commit | 707d33cb0b731472b7564d9fad8d45cbbd7fece3 (patch) | |
| tree | 763dca679d262fc8ec1a3222c0caac6500e92966 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 4.9-rc1 (diff) | |
| download | wireguard-linux-707d33cb0b731472b7564d9fad8d45cbbd7fece3.tar.xz wireguard-linux-707d33cb0b731472b7564d9fad8d45cbbd7fece3.zip | |
clk: hisilicon: add CRG driver for Hi3798CV200 SoC
Add CRG driver for Hi3798CV200 SoC. CRG(Clock and Reset
Generator) module generates clock and reset signals used
by other module blocks on SoC.
Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions