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| author |   Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-13 23:41:33 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2016-05-23 21:11:15 +0300 |
| commit | 709e05c3c46e866243f369a46ca5552a5c1e6b44 (patch) | |
| tree | 4bef1cb0c169fd57ff7107773e7a065aefa5512f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915: Rename skl_vco_freq to cdclk_pll.vco (diff) | |
| download | wireguard-linux-709e05c3c46e866243f369a46ca5552a5c1e6b44.tar.xz wireguard-linux-709e05c3c46e866243f369a46ca5552a5c1e6b44.zip | |
drm/i915: Store cdclk PLL reference clock under dev_priv
Future platforms will have multiple options for the cdclk PLL reference
clock, so let's start tracking that under dev_priv alreday on SKL,
although on SKL it's always 24 MHz.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-15-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions