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| author |   Sylvain Lemieux <slemieux@tycoint.com> | 2016-04-20 09:20:58 -0400 |
|---|---|---|
| committer |   Vladimir Zapolskiy <vz@mleia.com> | 2016-04-21 22:29:34 +0300 |
| commit | 73fdaa0f332fcf301327053cff7e523a85b0e7c7 (patch) | |
| tree | bbe7b0a4e3db0c9bb12bf5ca1ed13dc9a72f3fbb /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: lpc32xx: set default clock rate of HCLK PLL (diff) | |
| download | wireguard-linux-73fdaa0f332fcf301327053cff7e523a85b0e7c7.tar.xz wireguard-linux-73fdaa0f332fcf301327053cff7e523a85b0e7c7.zip | |
ARM: dts: lpc32xx: add clock properties to spi nodes
The change adds clock properties to spi peripheral devices,
clock ids are taken from dt-bindings/clock/lpc32xx-clock.h
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions