diff options
| author |   Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2024-08-28 13:41:27 +0100 |
|---|---|---|
| committer |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-09-02 11:23:57 +0200 |
| commit | 740cf2a2d6868a63a12e89c8dd92333b39fd1c7d (patch) | |
| tree | fc2f11f424f34c88d7c7513c82f0fa4fdb558c8e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge tag 'renesas-r9a09g057-dt-binding-defs-tag' into renesas-dts-for-v6.12 (diff) | |
| download | wireguard-linux-740cf2a2d6868a63a12e89c8dd92333b39fd1c7d.tar.xz wireguard-linux-740cf2a2d6868a63a12e89c8dd92333b39fd1c7d.zip | |
arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC
Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are
the list of blocks added:
- EXT CLKs
- 4X CA55
- SCIF
- PFC
- CPG
- SYS
- GIC
- ARMv8 Timer
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240828124134.188864-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions