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| author |   Måns Rullgård <mans@mansr.com> | 2015-11-02 02:03:36 +0000 |
|---|---|---|
| committer |   Wolfram Sang <wsa@the-dreams.de> | 2015-12-15 13:13:00 +0100 |
| commit | 75d31c2372e4a08319919b14bd160c48305373a1 (patch) | |
| tree | 080f7a0592d7b64798ee20fd6a5a2820ceddeb0e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | i2c: uniphier_f: error out if bus speed is zero (diff) | |
| download | wireguard-linux-75d31c2372e4a08319919b14bd160c48305373a1.tar.xz wireguard-linux-75d31c2372e4a08319919b14bd160c48305373a1.zip | |
i2c: xlr: add support for Sigma Designs controller variant
Sigma Designs chips use a variant of this controller with the following
differences:
- The BUSY bit in the STATUS register is inverted
- Bit 8 of the CONFIG register must be set
- The controller can generate interrupts
This patch adds support for the first two of these. It also calculates
and sets the correct clock divisor if a clk is provided. The bus
frequency is optionally speficied in the device tree node.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions