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| author |   Yash Shah <yash.shah@sifive.com> | 2020-12-08 10:25:33 +0530 |
|---|---|---|
| committer |   Palmer Dabbelt <palmerdabbelt@google.com> | 2021-01-07 17:37:24 -0800 |
| commit | 75e6d7248efccc2b13d0f3811b29d3e5cb04bcad (patch) | |
| tree | de17be73d6d80596bbbfa95cd693d4f77aaf513c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | RISC-V: sifive_l2_cache: Update L2 cache driver to support SiFive FU740 (diff) | |
| download | wireguard-linux-75e6d7248efccc2b13d0f3811b29d3e5cb04bcad.tar.xz wireguard-linux-75e6d7248efccc2b13d0f3811b29d3e5cb04bcad.zip | |
dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC
Add new compatible strings in cpus.yaml to support the E71 and U74 CPU
cores ("harts") that are present on FU740-C000 SoC.
Signed-off-by: Yash Shah <yash.shah@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions