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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 11:19:12 +0100 |
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| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-01-31 11:19:12 +0100 |
| commit | 775e7c4d36c3fda8d917588aa41f9b7d30598486 (patch) | |
| tree | 0e7c038bf5aa2f9fba257e61e5e0e86edc34b61b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: renesas: r9a07g043: Add clock and reset entries for CRU (diff) | |
| parent | dt-bindings: clock: Add R8A779H0 V4M CPG Core Clock Definitions (diff) | |
| download | wireguard-linux-775e7c4d36c3fda8d917588aa41f9b7d30598486.tar.xz wireguard-linux-775e7c4d36c3fda8d917588aa41f9b7d30598486.zip | |
Merge tag 'renesas-r8a779h0-dt-binding-defs-tag' into renesas-clk-for-v6.9
Renesas R-Car V4M DT Binding Definitions
Clock and Power Domain definitions for the Renesas R-Car V4M (R8A779H0)
SoC, shared by driver and DT source files.
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions