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| author |   Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2019-05-28 12:40:52 +0300 |
|---|---|---|
| committer |   Vineet Gupta <vgupta@synopsys.com> | 2019-05-28 10:06:42 -0700 |
| commit | 780b35b6aafcbbe24c36fa9ad6ba80e2dbe96632 (patch) | |
| tree | 4113dffe227ee9f6c3bb4807127b0b88de66073e /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARC: [plat-hsdk]: Add missing FIFO size entry in GMAC node (diff) | |
| download | wireguard-linux-780b35b6aafcbbe24c36fa9ad6ba80e2dbe96632.tar.xz wireguard-linux-780b35b6aafcbbe24c36fa9ad6ba80e2dbe96632.zip | |
ARC: [plat-hsdk]: enable creg-gpio controller
HSDK SOC has CREG GPIO controller which can be used to control
SPI chip select lines.
Enable it in preparation of enabling SPI peripherals.
Acked-by: Alexey Brodkin <abrodkin@synopsys.com>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions