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| author |   Chris Morgan <macromorgan@hotmail.com> | 2023-12-08 09:48:45 -0600 |
|---|---|---|
| committer |   Neil Armstrong <neil.armstrong@linaro.org> | 2023-12-11 10:12:59 +0100 |
| commit | 799825aa87200ade1ba21db853d1c2ff720dcfe0 (patch) | |
| tree | b9141f436e1b9b3637a4c683eebeea7c0d65106d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: display: panel: add Fascontek FS035VG158 panel (diff) | |
| download | wireguard-linux-799825aa87200ade1ba21db853d1c2ff720dcfe0.tar.xz wireguard-linux-799825aa87200ade1ba21db853d1c2ff720dcfe0.zip | |
drm/panel: st7701: Fix AVCL calculation
The AVCL register, according to the datasheet, comes in increments
of -0.2v between -4.4v (represented by 0x0) to -5.0v (represented
by 0x3). The current calculation is done by adding the defined
AVCL value in mV to -4400 and then dividing by 200 to get the register
value. Unfortunately if I subtract -4400 from -4400 I get -8800, which
divided by 200 gives me -44. If I instead subtract -4400 from -4400
I get 0, which divided by 200 gives me 0. Based on the datasheet this
is the expected register value.
Fixes: 83b7a8e7e88e ("drm/panel/panel-sitronix-st7701: Parametrize voltage and timing")
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231208154847.130615-2-macroalpha82@gmail.com
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20231208154847.130615-2-macroalpha82@gmail.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions