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author | 2019-05-11 10:27:34 -0400 | |
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committer | 2019-05-11 10:27:34 -0400 | |
commit | 7a5575212ce4b6a41581b92fe03b6be1134793ba (patch) | |
tree | f76ae29af196387330dd9a7c4a86200cbe80182c /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge tag 'docs-5.2a' of git://git.lwn.net/linux (diff) | |
parent | xtensa: implement initialize_cacheattr for MPU cores (diff) | |
download | wireguard-linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.tar.xz wireguard-linux-7a5575212ce4b6a41581b92fe03b6be1134793ba.zip |
Merge tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa
Pull xtensa updates from Max Filippov:
- implement atomic operations using exclusive access Xtensa option
operations
- add support for Xtensa cores with memory protection unit (MPU)
- clean up xtensa-specific kernel-only headers
- fix error path in simdisk_setup
* tag 'xtensa-20190510' of git://github.com/jcmvbkbc/linux-xtensa:
xtensa: implement initialize_cacheattr for MPU cores
xtensa: add exclusive atomics support
xtensa: clean up inline assembly in futex.h
xtensa: replace variant/core.h with asm/core.h
xtensa: drop ifdef __KERNEL__ from kernel-only headers
xtensa: set proper error code for simdisk_setup()
xtensa: fix incorrect fd close in error case of simdisk_setup()
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