diff options
| author |   Yakir Yang <ykk@rock-chips.com> | 2016-06-29 17:15:18 +0800 |
|---|---|---|
| committer | Yakir Yang <ykk@rock-chips.com> | 2016-07-05 09:16:40 +0800 |
| commit | 7bdc072086939093238a970f054e8e63d531253d (patch) | |
| tree | 196452ddb8620fedcebafb39e672d922b94d0875 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/bridge: analogix_dp: correct the register bit define error in ANALOGIX_DP_PLL_REG_1 (diff) | |
| download | wireguard-linux-7bdc072086939093238a970f054e8e63d531253d.tar.xz wireguard-linux-7bdc072086939093238a970f054e8e63d531253d.zip | |
drm/bridge: analogix_dp: some rockchip chips need to flip REF_CLK bit setting
As vendor document indicate, when REF_CLK bit set 0, then DP
phy's REF_CLK should switch to 24M source clock.
But due to IC PHY layout mistaken, some chips need to flip this
bit(like RK3288), and unfortunately they didn't indicate in the
DP version register. That's why we have to make this little hack.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Tomasz Figa <tomasz.figa@chromium.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions