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| author |   Drew Fustini <dfustini@tenstorrent.com> | 2024-08-01 11:38:09 -0700 |
|---|---|---|
| committer |   Drew Fustini <drew@pdp7.com> | 2024-08-08 09:19:46 -0700 |
| commit | 7f5b28218cec55072b562be386675ccae41acca1 (patch) | |
| tree | 427eb42c22202a5fe1d891dae64e0db05a299665 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller (diff) | |
| download | wireguard-linux-7f5b28218cec55072b562be386675ccae41acca1.tar.xz wireguard-linux-7f5b28218cec55072b562be386675ccae41acca1.zip | |
riscv: dts: thead: add clock to TH1520 gpio nodes
Add clock property to TH1520 gpio controller nodes. These clock gates
refer to corresponding enable bits in the peripheral clock gate control
register. Refer to register PERI_CLK_CFG in section 4.4.2.2.52 of the
TH1520 System User Manual.
Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions