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author | 2024-05-16 18:14:09 -0500 | |
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committer | 2024-05-16 18:14:09 -0500 | |
commit | 83711a1ab210cf59d30a3e65f72268f5404c1870 (patch) | |
tree | 65f9202cc2aa46c84b87f4c4f71d76eb3f388f01 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | Merge branch 'pci/aspm' (diff) | |
parent | cxl: Add post-reset warning if reset results in loss of previously committed HDM decoders (diff) | |
download | wireguard-linux-83711a1ab210cf59d30a3e65f72268f5404c1870.tar.xz wireguard-linux-83711a1ab210cf59d30a3e65f72268f5404c1870.zip |
Merge branch 'pci/cxl'
- Lock the upstream bridge while using it to perform a Secondary Bus Reset
(Dave Jiang)
- Return failure when attempting Secondary Bus Reset below a CXL Port that
has SBR masked (Dave Jiang)
- Add a "cxl_bus" reset method that temporarily unmasks SBR (Dave Jiang)
- Add a warning if we reset a CXL type 3 memory device that was in use
while being reset (Dave Jiang)
* pci/cxl:
cxl: Add post-reset warning if reset results in loss of previously committed HDM decoders
PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports
PCI/CXL: Fail bus reset if upstream CXL Port has SBR masked
PCI: Lock upstream bridge for pci_reset_function()
PCI/CXL: Move CXL Vendor ID to pci_ids.h
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions