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| author |   Vignesh R <vigneshr@ti.com> | 2018-10-15 12:08:29 +0530 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2018-10-19 13:32:59 +0100 |
| commit | 89e8b9cb846515e4435eb42df7009b824cf3405a (patch) | |
| tree | 9c343b293daa2f965ac05c100a69676e14db82da /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | spi: omap2-mcspi: Set FIFO DMA trigger level to word length (diff) | |
| download | wireguard-linux-89e8b9cb846515e4435eb42df7009b824cf3405a.tar.xz wireguard-linux-89e8b9cb846515e4435eb42df7009b824cf3405a.zip | |
spi: omap2-mcspi: Add slave mode support
Add support to use McSPI controller as SPI slave. In slave mode, DMA TX
completion does not mean entire data has been shifted out as data might
still be stuck in FIFO waiting for master to clock the bus. Therefore,
add an IRQ handler for slave mode to know when entire data in FIFO has
been shifted out.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions