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| author |   Cristian Ciocaltea <cristian.ciocaltea@collabora.com> | 2023-04-02 12:50:52 +0300 |
|---|---|---|
| committer |   Heiko Stuebner <heiko@sntech.de> | 2023-04-05 19:30:20 +0200 |
| commit | 8ae112a5554fb1580fc5564f8610cef85f2e3f7b (patch) | |
| tree | b33801a7049df15111056bb8a75922f555c8c098 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | arm64: dts: rockchip: Assign PLL_PPLL clock rate to 1.1 GHz on rk3588s (diff) | |
| download | wireguard-linux-8ae112a5554fb1580fc5564f8610cef85f2e3f7b.tar.xz wireguard-linux-8ae112a5554fb1580fc5564f8610cef85f2e3f7b.zip | |
arm64: dts: rockchip: Add rk3588s I2S nodes
There are five I2S/PCM/TDM controllers and two I2S/PCM controllers
embedded in the RK3588 and RK3588S SoCs.
Add the DT nodes corresponding to the above mentioned Rockchip
controllers.
Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers,
which are handled via a separate patch.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Link: https://lore.kernel.org/r/20230402095054.384739-4-cristian.ciocaltea@collabora.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions