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| author |   Thippeswamy Havalige <thippeswamy.havalige@amd.com> | 2023-10-03 23:04:53 +0530 |
|---|---|---|
| committer |   Krzysztof Wilczyński <kwilczynski@kernel.org> | 2023-10-26 15:02:02 +0000 |
| commit | 8d786149d78c7784144c7179e25134b6530b714b (patch) | |
| tree | 6029c56291d0a559673c3a51222fa3308ab7d4ee /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: PCI: xilinx-xdma: Add schemas for Xilinx XDMA PCIe Root Port Bridge (diff) | |
| download | wireguard-linux-8d786149d78c7784144c7179e25134b6530b714b.tar.xz wireguard-linux-8d786149d78c7784144c7179e25134b6530b714b.zip | |
PCI: xilinx-xdma: Add Xilinx XDMA Root Port driver
Add support for Xilinx XDMA Soft IP core as Root Port.
The Zynq UltraScale+ MPSoCs devices support XDMA soft IP module in
programmable logic.
The integrated XDMA Soft IP block has integrated bridge function that
can act as PCIe Root Port.
[kwilczynski: correct indentation and whitespaces, Kconfig help update]
Link: https://lore.kernel.org/linux-pci/20231003173453.938190-4-thippeswamy.havalige@amd.com
Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@amd.com>
Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@amd.com>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions