diff options
| author |   Stephen Boyd <sboyd@kernel.org> | 2023-12-13 15:26:24 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-12-13 15:26:24 -0800 |
| commit | 8defec031c40913ef10d2f654a5ccc8a2a9730c1 (patch) | |
| tree | e1493c4ab0eb274877fddc28bf92db1f8c930457 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | clk: qcom: Fix SM_CAMCC_8550 dependencies (diff) | |
| parent | clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name (diff) | |
| download | wireguard-linux-8defec031c40913ef10d2f654a5ccc8a2a9730c1.tar.xz wireguard-linux-8defec031c40913ef10d2f654a5ccc8a2a9730c1.zip | |
Merge tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes
Pull Rockchip clk driver fixes for the merge window from Heiko Stuebner:
Fixes for a wrong clockname, a wrong clock-parent, a wrong clock-gate
and finally one new PLL rate for the rk3568 to fix display artifacts
on a handheld devices based on that soc.
* tag 'v6.7-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name
clk: rockchip: rk3128: Fix aclk_peri_src's parent
clk: rockchip: rk3128: Fix HCLK_OTG gate register
clk: rockchip: rk3568: Add PLL rate for 292.5MHz
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions