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| author |   Eric Yang <Eric.Yang2@amd.com> | 2020-05-29 17:13:57 -0400 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2020-07-01 01:59:25 -0400 |
| commit | 8f95ff284cd2b3be0ee49d2c7b29d408aad3843d (patch) | |
| tree | 015ec3b83262e2589af77f6c249b1febd919dbd4 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/display: fine tune logic of edid max TMDS clock check (diff) | |
| download | wireguard-linux-8f95ff284cd2b3be0ee49d2c7b29d408aad3843d.tar.xz wireguard-linux-8f95ff284cd2b3be0ee49d2c7b29d408aad3843d.zip | |
drm/amd/display: add mechanism to skip DCN init
[Why]
If optimized init is done in FW. DCN init be skipped in driver. This
need to be communicated between driver and fw and maintain backwards
compatibility.
[How]
Use DMUB scratch 0 bit 2 to indicate optimized init done in fw and
use DMUB scatch 4 bit 0 to indicate drive supports the optimized flow
so FW will perform it.
Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions