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| author |   Bjorn Helgaas <bhelgaas@google.com> | 2023-04-20 16:16:32 -0500 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-04-20 16:16:32 -0500 |
| commit | 90d66d4d86aee7a6a429081c9d95e663463ab436 (patch) | |
| tree | 61e17d5a31a3e7d34f45fec79398ddaac6f0512f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branch 'pci/aer' (diff) | |
| parent | PCI: Fix up L1SS capability for Intel Apollo Lake Root Port (diff) | |
| download | wireguard-linux-90d66d4d86aee7a6a429081c9d95e663463ab436.tar.xz wireguard-linux-90d66d4d86aee7a6a429081c9d95e663463ab436.zip | |
Merge branch 'pci/aspm'
- Work around Chromebook firmware issue that corrupts Extended Capability
list (including L1 PM Substates capability) on D3cold -> D0 transitions
(Ron Lee)
* pci/aspm:
PCI: Fix up L1SS capability for Intel Apollo Lake Root Port
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions