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| author |   Icenowy Zheng <icenowy@aosc.io> | 2020-09-23 08:58:54 +0800 |
|---|---|---|
| committer |   Maxime Ripard <maxime@cerno.tech> | 2020-09-28 12:09:22 +0200 |
| commit | 90e048101fa192e6e1ea48192fa22d8c684a0bf1 (patch) | |
| tree | 203dad0ace1b71c45b2481a47297a9cef4b0eb65 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: sun8i: V3/V3s/S3/S3L: add pinctrl for UART2 RX/TX (diff) | |
| download | wireguard-linux-90e048101fa192e6e1ea48192fa22d8c684a0bf1.tar.xz wireguard-linux-90e048101fa192e6e1ea48192fa22d8c684a0bf1.zip | |
ARM: dts: sun8i: V3/V3s/S3/S3L: add CSI1 device node
The CSI1 controller of V3/V3s/S3/S3L chips is used for parallel CSI.
Add the device tree node of it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Link: https://lore.kernel.org/r/20200923005858.148261-2-icenowy@aosc.io
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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