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| author |   Linu Cherian <lcherian@marvell.com> | 2025-02-12 17:19:12 +0530 |
|---|---|---|
| committer |   Suzuki K Poulose <suzuki.poulose@arm.com> | 2025-02-21 16:16:54 +0000 |
| commit | 91a2086aa6d1558da427e2539eb20a9d6b352361 (patch) | |
| tree | 2227549817571a5db57e440a6ce44447c4fa6b3d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | dt-bindings: arm: coresight-tmc: Add "memory-region" property (diff) | |
| download | wireguard-linux-91a2086aa6d1558da427e2539eb20a9d6b352361.tar.xz wireguard-linux-91a2086aa6d1558da427e2539eb20a9d6b352361.zip | |
coresight: tmc-etr: Add support to use reserved trace memory
Add support to use reserved memory for coresight ETR trace buffer.
Introduce a new ETR buffer mode called ETR_MODE_RESRV, which
becomes available when ETR device tree node is supplied with a valid
reserved memory region.
ETR_MODE_RESRV can be selected only by explicit user request.
$ echo resrv >/sys/bus/coresight/devices/tmc_etr<N>/buf_mode_preferred
Signed-off-by: Anil Kumar Reddy <areddy3@marvell.com>
Signed-off-by: Linu Cherian <lcherian@marvell.com>
Reviewed-by: James Clark <james.clark@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250212114918.548431-3-lcherian@marvell.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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