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| author |   Aaron Brice <aaron.brice@datasoft.com> | 2015-04-03 13:39:31 -0700 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2015-04-06 18:12:25 +0100 |
| commit | 95bf15f386417f3ba80bb860c1385b1ebfdcdffa (patch) | |
| tree | 61b3f2885d7c8f8d3a7cbe2c36fd1bd7b001498a /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | spi: fsl-dspi: Add cs-sck delays (diff) | |
| download | wireguard-linux-95bf15f386417f3ba80bb860c1385b1ebfdcdffa.tar.xz wireguard-linux-95bf15f386417f3ba80bb860c1385b1ebfdcdffa.zip | |
spi: fsl-dspi: Add ~50ns delay between cs and sck
Add delay between chip select and clock signals, before clock starts and
after clock stops.
Signed-off-by: Aaron Brice <aaron.brice@datasoft.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions