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| author |   Bard Liao <bardliao@realtek.com> | 2014-11-06 12:23:54 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2014-11-06 06:01:13 +0000 |
| commit | 96927ac96d7658b35a4f0f3dcdb8c6b74472a3ea (patch) | |
| tree | b16323defe4b69d55f9414dce7018754edcc34b8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: rt5670: correct the incorrect default values (diff) | |
| download | wireguard-linux-96927ac96d7658b35a4f0f3dcdb8c6b74472a3ea.tar.xz wireguard-linux-96927ac96d7658b35a4f0f3dcdb8c6b74472a3ea.zip | |
ASoC: rt5670: change dapm routes of PLL connection
PLL should be powered up once filter power is on. So, "PLL1"
should be connected to filters instead of DACs.
Signed-off-by: Bard Liao <bardliao@realtek.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions