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| author |   Clark Wang <xiaoning.wang@nxp.com> | 2023-05-05 14:35:57 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2023-05-23 19:22:45 +0100 |
| commit | 9728fb3ce11729aa8c276825ddf504edeb00611d (patch) | |
| tree | 814ba49686bc5d2c56bb532917a8a47773d7b615 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | spi: spi-cadence: Interleave write of TX and read of RX FIFO (diff) | |
| download | wireguard-linux-9728fb3ce11729aa8c276825ddf504edeb00611d.tar.xz wireguard-linux-9728fb3ce11729aa8c276825ddf504edeb00611d.zip | |
spi: lpspi: disable lpspi module irq in DMA mode
When all bits of IER are set to 0, we still can observe the lpspi irq events
when using DMA mode to transfer data.
So disable irq to avoid the too much irq events.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Link: https://lore.kernel.org/r/20230505063557.3962220-1-xiaoning.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions