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| author |   Zhang Qilong <zhangqilong3@huawei.com> | 2022-09-29 00:04:02 +0800 |
|---|---|---|
| committer |   Mark Brown <broonie@kernel.org> | 2022-11-29 17:31:43 +0000 |
| commit | 97b801be6f8e53676b9f2b105f54e35c745c1b22 (patch) | |
| tree | 802c21ba5398f161e08c843b0dd72575eb28af5b /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ASoC: Intel: avs: Refactor jack handling (diff) | |
| download | wireguard-linux-97b801be6f8e53676b9f2b105f54e35c745c1b22.tar.xz wireguard-linux-97b801be6f8e53676b9f2b105f54e35c745c1b22.zip | |
ASoC: pcm512x: Fix PM disable depth imbalance in pcm512x_probe
The pm_runtime_enable will increase power disable depth. Thus
a pairing decrement is needed on the error handling path to
keep it balanced according to context. We fix it by going to
err_pm instead of err_clk.
Fixes:f086ba9d5389c ("ASoC: pcm512x: Support mastering BCLK/LRCLK using the PLL")
Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com>
Link: https://lore.kernel.org/r/20220928160402.126140-1-zhangqilong3@huawei.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions