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| author |   Tian Tao <tiantao6@hisilicon.com> | 2020-10-19 08:43:13 +0800 |
|---|---|---|
| committer |   Ulf Hansson <ulf.hansson@linaro.org> | 2020-11-16 11:59:28 +0100 |
| commit | 9baf7c5e3ab364c038070a3b396de3b8a10016cd (patch) | |
| tree | 669ca88dc120381066424081b17b8403c85cad06 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | mmc: mediatek: Add subsys clock control for MT8192 msdc (diff) | |
| download | wireguard-linux-9baf7c5e3ab364c038070a3b396de3b8a10016cd.tar.xz wireguard-linux-9baf7c5e3ab364c038070a3b396de3b8a10016cd.zip | |
mmc: mediatek: Replace spin_lock_irqsave by spin_lock in hard IRQ
The code has been in a irq-disabled context since it is hard IRQ. Therefore
there no need to do it again.
Signed-off-by: Tian Tao <tiantao6@hisilicon.com>
Link: https://lore.kernel.org/r/1603068193-44688-1-git-send-email-tiantao6@hisilicon.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions