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| author |   Koji Matsuoka <koji.matsuoka.xm@renesas.com> | 2016-04-18 16:31:30 +0900 |
|---|---|---|
| committer |   Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> | 2016-11-15 01:44:50 +0200 |
| commit | 9cdced8a39c04cf798ddb2a27cb5952f7d39f633 (patch) | |
| tree | e00c8f9060a77501295b6c6ba8de5a1c96d5e84f /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm: rcar-du: Fix dot clock routing configuration (diff) | |
| download | wireguard-linux-9cdced8a39c04cf798ddb2a27cb5952f7d39f633.tar.xz wireguard-linux-9cdced8a39c04cf798ddb2a27cb5952f7d39f633.zip | |
drm: rcar-du: Fix display timing controller parameter
There is a bug in the setting of the DES (Display Enable Signal)
register. This current setting occurs 1 dot left shift. The DES
register should be set minus one value about the specifying value
with H/W specification. This patch corrects it.
Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions