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authorEric Yang <Eric.Yang2@amd.com>2019-11-05 11:59:38 -0500
committerAlex Deucher <alexander.deucher@amd.com>2019-12-05 17:55:32 -0500
commit9d9de889ff8eb941e4daefff610e170386b61962 (patch)
tree3b7e7510ef2ae0a7e246d99f80c65cad003da983 /tools/perf/scripts/python/export-to-postgresql.py
parentdrm/amdgpu: add cache flush workaround to gfx8 emit_fence (diff)
downloadwireguard-linux-9d9de889ff8eb941e4daefff610e170386b61962.tar.xz
wireguard-linux-9d9de889ff8eb941e4daefff610e170386b61962.zip
drm/amd/display: update sr and pstate latencies for Renoir
[Why] DF team has produced more optimized latency numbers. [How] Add sr latencies to the wm table, use different latencies for different wm sets. Also fix bb override from registery key for these latencies. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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