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| author |   Clark Wang <xiaoning.wang@nxp.com> | 2024-10-30 17:39:21 +0800 |
|---|---|---|
| committer |   David S. Miller <davem@davemloft.net> | 2024-11-04 10:03:51 +0000 |
| commit | 9e7f2116199d5b88e9fa6375a3b3aba4c6e08895 (patch) | |
| tree | 5d4d8dd4c1aca4b3c7ec12e5b8dafb6071166c78 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | net: enetc: extract enetc_int_vector_init/destroy() from enetc_alloc_msix() (diff) | |
| download | wireguard-linux-9e7f2116199d5b88e9fa6375a3b3aba4c6e08895.tar.xz wireguard-linux-9e7f2116199d5b88e9fa6375a3b3aba4c6e08895.zip | |
net: enetc: optimize the allocation of tx_bdr
There is a situation where num_tx_rings cannot be divided by bdr_int_num.
For example, num_tx_rings is 8 and bdr_int_num is 3. According to the
previous logic, this results in two tx_bdr corresponding memories not
being allocated, so when sending packets to tx ring 6 or 7, wild pointers
will be accessed. Of course, this issue doesn't exist on LS1028A, because
its num_tx_rings is 8, and bdr_int_num is either 1 or 2. However, there
is a risk for the upcoming i.MX95. Therefore, it is necessary to ensure
that each tx_bdr can be allocated to the corresponding memory.
Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
Signed-off-by: Wei Fang <wei.fang@nxp.com>
Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions