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| author |   Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 17:40:41 +0100 |
|---|---|---|
| committer |   Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 07:45:12 +0100 |
| commit | a0504f0880c11da301dc2b5a5135bd02376e367e (patch) | |
| tree | a00ac8116bf946bf5b2f5bd9200d2e1cc58c45b7 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: r8a7791: Remove unit-address and reg from integrated cache (diff) | |
| download | wireguard-linux-a0504f0880c11da301dc2b5a5135bd02376e367e.tar.xz wireguard-linux-a0504f0880c11da301dc2b5a5135bd02376e367e.zip | |
ARM: dts: r8a7792: Remove unit-address and reg from integrated cache
The Cortex-A15 cache controller is an integrated controller, and thus
the device node representing it should not have a unit-addresses or reg
property.
Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions