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| author |   Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> | 2017-12-09 16:59:15 +0300 |
|---|---|---|
| committer |   Vineet Gupta <vgupta@synopsys.com> | 2017-12-20 12:41:44 -0800 |
| commit | a08c832f277d7a6f9d3b341a5d5df2f5576220d8 (patch) | |
| tree | 904c7baed42e96d959eaaa26c943abf4b95ee0c8 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARC: [plat-hsdk] Switch DisplayLink driver from fbdev to DRM (diff) | |
| download | wireguard-linux-a08c832f277d7a6f9d3b341a5d5df2f5576220d8.tar.xz wireguard-linux-a08c832f277d7a6f9d3b341a5d5df2f5576220d8.zip | |
ARC: [plat-hsdk]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions