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author | 2022-01-29 20:36:39 +0100 | |
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committer | 2022-02-01 09:17:16 +0100 | |
commit | a0d5455330ece6f50ddf9e71d530f91c302803e9 (patch) | |
tree | f5f9f8dde3b477497e433b4ba9e317f57bd0d528 /tools/perf/scripts/python/export-to-postgresql.py | |
parent | arm64: dts: exynos: drop unneeded syscon phandle in Exynos5433 LPASS (diff) | |
download | wireguard-linux-a0d5455330ece6f50ddf9e71d530f91c302803e9.tar.xz wireguard-linux-a0d5455330ece6f50ddf9e71d530f91c302803e9.zip |
arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7
Use the same order of USB 3.0 DRD controller clocks as in Exynos5433.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20220129193646.372481-1-krzysztof.kozlowski@canonical.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
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