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| author |   Dan Williams <dan.j.williams@intel.com> | 2022-11-29 10:48:42 -0700 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2022-12-03 13:40:17 -0800 |
| commit | a1554e9cac5ea04aaf2fb2de0df9936a94cb96fc (patch) | |
| tree | cff52081d64406c4ffa914c7eddad07843d7aa2c /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | cxl/port: Limit the port driver to just the HDM Decoder Capability (diff) | |
| download | wireguard-linux-a1554e9cac5ea04aaf2fb2de0df9936a94cb96fc.tar.xz wireguard-linux-a1554e9cac5ea04aaf2fb2de0df9936a94cb96fc.zip | |
cxl/pci: Prepare for mapping RAS Capability Structure
The RAS Capabilitiy Structure is a CXL Component register capability
block. Unlike the HDM Decoder Capability, it will be referenced by the
cxl_pci driver in response to PCIe AER events. Due to this it is no
longer the case that cxl_map_component_regs() can assume that it should
map all component registers. Plumb a bitmask of capability ids to map
through cxl_map_component_regs().
For symmetry cxl_probe_device_regs() is updated to populate @id in
'struct cxl_reg_map' even though cxl_map_device_regs() does not have a
need to map a subset of the device registers per caller.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/166974412214.1608150.11487843455070795378.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions