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| author |   Manasi Navare <manasi.d.navare@intel.com> | 2019-12-27 19:12:04 -0800 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2019-12-30 00:16:07 -0800 |
| commit | a3d9382bd439e7be1858abc3d5f014dd55913448 (patch) | |
| tree | 4ee9d32bca3e1355e66e9ba22777c42c1c0feed3 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/i915/dp: Make port sync mode assignments only if all tiles present (diff) | |
| download | wireguard-linux-a3d9382bd439e7be1858abc3d5f014dd55913448.tar.xz wireguard-linux-a3d9382bd439e7be1858abc3d5f014dd55913448.zip | |
drm/i915/dp: Disable Port sync mode correctly on teardown
While clearing the Ports ync mode enable and master select bits
we need to clear the register completely instead of using disable masks
v3:
* Remove reg variable (Matt)
v2:
* Just write 0 to the reg (Ville)
* Rebase
Bugzilla: https://gitlab.freedesktop.org/drm/intel/issues/5
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Fixes: 51528afe7c5e ("drm/i915/display/icl: Disable transcoder port sync as part of crtc_disable() sequence")
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191228031204.10189-3-manasi.d.navare@intel.com
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions