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| author |   Thor Thayer <tthayer@opensource.altera.com> | 2016-03-31 18:48:07 +0000 |
|---|---|---|
| committer |   Dinh Nguyen <dinguyen@kernel.org> | 2016-04-11 14:03:41 -0500 |
| commit | a44a77115f76a7dd7de4396a7ba159eed1d8be21 (patch) | |
| tree | 25c01efb2bfb391cdc4ae69d311f05d41e79628d /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry (diff) | |
| download | wireguard-linux-a44a77115f76a7dd7de4396a7ba159eed1d8be21.tar.xz wireguard-linux-a44a77115f76a7dd7de4396a7ba159eed1d8be21.zip | |
ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entry
Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions