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| author |   Stephen Boyd <sboyd@kernel.org> | 2024-01-09 11:55:06 -0800 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-01-09 11:55:06 -0800 |
| commit | a4dcb2f84be44da9e7ae0e420adcab1f6efb8de6 (patch) | |
| tree | 8ff9da7196acf38b4f571095498763cd704911b2 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Merge branches 'clk-imx', 'clk-qcom', 'clk-amlogic' and 'clk-mediatek' into clk-next (diff) | |
| parent | drivers: clk: zynqmp: update divider round rate logic (diff) | |
| parent | clocking-wizard: Add support for versal clocking wizard (diff) | |
| parent | dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform (diff) | |
| download | wireguard-linux-a4dcb2f84be44da9e7ae0e420adcab1f6efb8de6.tar.xz wireguard-linux-a4dcb2f84be44da9e7ae0e420adcab1f6efb8de6.zip | |
Merge branches 'clk-zynq', 'clk-xilinx' and 'clk-stm' into clk-next
- Update Zynqmp driver for Versal NET platforms
- Add clk driver for Versal clocking wizard IP
* clk-zynq:
drivers: clk: zynqmp: update divider round rate logic
drivers: clk: zynqmp: calculate closest mux rate
* clk-xilinx:
clocking-wizard: Add support for versal clocking wizard
dt-bindings: clock: xilinx: add versal compatible
* clk-stm:
dt-bindings: stm32: add clocks and reset binding for stm32mp25 platform
clk: stm32mp1: use stm32mp13 reset driver
clk: stm32mp1: move stm32mp1 clock driver into stm32 directory