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| author |   Rex Zhu <Rex.Zhu@amd.com> | 2016-07-20 18:40:09 +0800 |
|---|---|---|
| committer |   Alex Deucher <alexander.deucher@amd.com> | 2016-07-29 14:36:59 -0400 |
| commit | a93d54d842ac5d1502fce65d8d937a41a45245af (patch) | |
| tree | cbeca16eeaf34ff19d27cc445181d65eeb2c98c0 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | drm/amd/powerplay: fix typo error when set clock gate state. (diff) | |
| download | wireguard-linux-a93d54d842ac5d1502fce65d8d937a41a45245af.tar.xz wireguard-linux-a93d54d842ac5d1502fce65d8d937a41a45245af.zip | |
Revert "drm/amd/powerplay: workaround issue that when uvd dpm disabled,"
This reverts commit <2ded8c7f04825bc5cde2624f6aa83f1ff62672c0>
As we enabled bypass mode for uvd on polaris10 when clockgating.
so no need to set uvd clock manually.
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Christian König<christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions