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| author |   Stephen Boyd <sboyd@kernel.org> | 2019-04-19 13:20:58 -0700 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2019-04-19 13:20:58 -0700 |
| commit | aa2a0592ceb65bcba5fa1b8d9a7fb8c43d7cadb9 (patch) | |
| tree | 041395168f069b9e5b1cfe7440a4e9e8069cda57 /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | Linux 5.1-rc1 (diff) | |
| parent | clk: samsung: exynos5410: Add gate clock for ADC (diff) | |
| download | wireguard-linux-aa2a0592ceb65bcba5fa1b8d9a7fb8c43d7cadb9.tar.xz wireguard-linux-aa2a0592ceb65bcba5fa1b8d9a7fb8c43d7cadb9.zip | |
Merge tag 'clk-v5.2-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk into clk-samsung
Pull Samsung clk driver updates from Sylwester Nawrocki:
- Addition of ADC clock definition for Exynos 5410 SoC (Odroid XU)
* tag 'clk-v5.2-samsung' of https://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk:
clk: samsung: exynos5410: Add gate clock for ADC
clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410
clk: samsung: dt-bindings: Put CLK_UART3 in order
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions