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| author |   Samuel Holland <samuel.holland@sifive.com> | 2024-03-26 21:49:43 -0700 |
|---|---|---|
| committer |   Palmer Dabbelt <palmer@rivosinc.com> | 2024-04-29 10:49:25 -0700 |
| commit | aaa56c8f378dd798f4a7f633cbf2eb129e98e6a4 (patch) | |
| tree | 5c910bc75769690d20f15587d91c780ec8028bba /tools/perf/scripts/python/export-to-postgresql.py | |
| parent | riscv: Flush the instruction cache during SMP bringup (diff) | |
| download | wireguard-linux-aaa56c8f378dd798f4a7f633cbf2eb129e98e6a4.tar.xz wireguard-linux-aaa56c8f378dd798f4a7f633cbf2eb129e98e6a4.zip | |
riscv: Factor out page table TLB synchronization
The logic is the same for all page table levels. See commit 69be3fb111e7
("riscv: enable MMU_GATHER_RCU_TABLE_FREE for SMP && MMU").
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/20240327045035.368512-3-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'tools/perf/scripts/python/export-to-postgresql.py')
0 files changed, 0 insertions, 0 deletions